diff --git a/arch/arm/dts/r8a7790-lager-u-boot.dts b/arch/arm/dts/r8a7790-lager-u-boot.dts
index 8a37cb9..fecf7e7 100644
--- a/arch/arm/dts/r8a7790-lager-u-boot.dts
+++ b/arch/arm/dts/r8a7790-lager-u-boot.dts
@@ -11,3 +11,10 @@
 &scif0 {
 	u-boot,dm-pre-reloc;
 };
+
+&qspi {
+	flash@0 {
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+	};
+};
diff --git a/arch/arm/dts/r8a7790-stout-u-boot.dts b/arch/arm/dts/r8a7790-stout-u-boot.dts
index 4798265..1396764 100644
--- a/arch/arm/dts/r8a7790-stout-u-boot.dts
+++ b/arch/arm/dts/r8a7790-stout-u-boot.dts
@@ -11,3 +11,10 @@
 &scifa0 {
 	u-boot,dm-pre-reloc;
 };
+
+&qspi {
+	flash@0 {
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+	};
+};
diff --git a/arch/arm/dts/r8a7791-koelsch-u-boot.dts b/arch/arm/dts/r8a7791-koelsch-u-boot.dts
index 85a5290..4a98528 100644
--- a/arch/arm/dts/r8a7791-koelsch-u-boot.dts
+++ b/arch/arm/dts/r8a7791-koelsch-u-boot.dts
@@ -11,3 +11,10 @@
 &scif0 {
 	u-boot,dm-pre-reloc;
 };
+
+&qspi {
+	flash@0 {
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+	};
+};
diff --git a/arch/arm/dts/r8a7791-porter-u-boot.dts b/arch/arm/dts/r8a7791-porter-u-boot.dts
index 275f6b4..82051be 100644
--- a/arch/arm/dts/r8a7791-porter-u-boot.dts
+++ b/arch/arm/dts/r8a7791-porter-u-boot.dts
@@ -16,3 +16,10 @@
 	status = "okay";
 	clock-frequency = <400000>;
 };
+
+&qspi {
+	flash@0 {
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+	};
+};
diff --git a/arch/arm/dts/r8a7793-gose-u-boot.dts b/arch/arm/dts/r8a7793-gose-u-boot.dts
index d8e072c..a35d35c 100644
--- a/arch/arm/dts/r8a7793-gose-u-boot.dts
+++ b/arch/arm/dts/r8a7793-gose-u-boot.dts
@@ -11,3 +11,10 @@
 &scif0 {
 	u-boot,dm-pre-reloc;
 };
+
+&qspi {
+	flash@0 {
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+	};
+};
diff --git a/arch/arm/dts/r8a7794-alt-u-boot.dts b/arch/arm/dts/r8a7794-alt-u-boot.dts
index e6ef23d..593a418 100644
--- a/arch/arm/dts/r8a7794-alt-u-boot.dts
+++ b/arch/arm/dts/r8a7794-alt-u-boot.dts
@@ -11,3 +11,10 @@
 &scif2 {
 	u-boot,dm-pre-reloc;
 };
+
+&qspi {
+	flash@0 {
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+	};
+};
diff --git a/arch/arm/dts/r8a7794-silk-u-boot.dts b/arch/arm/dts/r8a7794-silk-u-boot.dts
index 0e104aa..179753d 100644
--- a/arch/arm/dts/r8a7794-silk-u-boot.dts
+++ b/arch/arm/dts/r8a7794-silk-u-boot.dts
@@ -11,3 +11,10 @@
 &scif2 {
 	u-boot,dm-pre-reloc;
 };
+
+&qspi {
+	flash@0 {
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+	};
+};
diff --git a/arch/arm/dts/r8a77965-u-boot.dtsi b/arch/arm/dts/r8a77965-u-boot.dtsi
index cbd29b3..ca80ef8 100644
--- a/arch/arm/dts/r8a77965-u-boot.dtsi
+++ b/arch/arm/dts/r8a77965-u-boot.dtsi
@@ -19,103 +19,4 @@
 		bank-width = <2>;
 		status = "disabled";
 	};
-
-	sdhi0: sd@ee100000 {
-		compatible = "renesas,sdhi-r8a77965";
-		reg = <0 0xee100000 0 0x2000>;
-		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cpg CPG_MOD 314>;
-		max-frequency = <200000000>;
-		power-domains = <&sysc 32>;
-		resets = <&cpg 314>;
-		status = "disabled";
-	};
-
-	sdhi1: sd@ee120000 {
-		compatible = "renesas,sdhi-r8a77965";
-		reg = <0 0xee120000 0 0x2000>;
-		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cpg CPG_MOD 313>;
-		max-frequency = <200000000>;
-		power-domains = <&sysc 32>;
-		resets = <&cpg 313>;
-		status = "disabled";
-	};
-
-	sdhi2: sd@ee140000 {
-		compatible = "renesas,sdhi-r8a77965";
-		reg = <0 0xee140000 0 0x2000>;
-		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cpg CPG_MOD 312>;
-		max-frequency = <200000000>;
-		power-domains = <&sysc 32>;
-		resets = <&cpg 312>;
-		status = "disabled";
-	};
-
-	sdhi3: sd@ee160000 {
-		compatible = "renesas,sdhi-r8a77965";
-		reg = <0 0xee160000 0 0x2000>;
-		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cpg CPG_MOD 311>;
-		max-frequency = <200000000>;
-		power-domains = <&sysc 32>;
-		resets = <&cpg 311>;
-		status = "disabled";
-	};
-
-	ehci0: usb@ee080100 {
-		compatible = "generic-ehci";
-		reg = <0 0xee080100 0 0x100>;
-		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cpg CPG_MOD 703>;
-		phys = <&usb2_phy0>;
-		phy-names = "usb";
-		companion= <&ohci0>;
-		power-domains = <&sysc 32>;
-		resets = <&cpg 703>;
-	};
-
-	usb2_phy0: usb-phy@ee080200 {
-		compatible = "renesas,usb2-phy-r8a77965",
-			     "renesas,rcar-gen3-usb2-phy";
-		reg = <0 0xee080200 0 0x700>;
-		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cpg CPG_MOD 703>;
-		power-domains = <&sysc 32>;
-		resets = <&cpg 703>;
-		#phy-cells = <0>;
-	};
-
-	ehci1: usb@ee0a0100 {
-		compatible = "generic-ehci";
-		reg = <0 0xee0a0100 0 0x100>;
-		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cpg CPG_MOD 702>;
-		phys = <&usb2_phy1>;
-		phy-names = "usb";
-		companion= <&ohci1>;
-		power-domains = <&sysc 32>;
-		resets = <&cpg 702>;
-	};
-
-	usb2_phy1: usb-phy@ee0a0200 {
-		compatible = "renesas,usb2-phy-r8a77965",
-			     "renesas,rcar-gen3-usb2-phy";
-		reg = <0 0xee0a0200 0 0x700>;
-		clocks = <&cpg CPG_MOD 702>;
-		power-domains = <&sysc 32>;
-		resets = <&cpg 702>;
-		#phy-cells = <0>;
-	};
-
-	xhci0: usb@ee000000 {
-		compatible = "renesas,xhci-r8a77965",
-			     "renesas,rcar-gen3-xhci";
-		reg = <0 0xee000000 0 0xc00>;
-		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cpg CPG_MOD 328>;
-		power-domains = <&sysc 32>;
-		resets = <&cpg 328>;
-	};
 };
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index fcf211d..ec8339e 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -62,8 +62,8 @@
 	/* Disable the L2 cache */
 	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 
-	writel(0x111, &pl310->pl310_tag_latency_ctrl);
-	writel(0x121, &pl310->pl310_data_latency_ctrl);
+	writel(0x0, &pl310->pl310_tag_latency_ctrl);
+	writel(0x10, &pl310->pl310_data_latency_ctrl);
 
 	/* enable BRESP, instruction and data prefetch, full line of zeroes */
 	setbits_le32(&pl310->pl310_aux_ctrl,
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index c97eacb..c8e73d4 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -77,6 +77,8 @@
 
 void board_init_f(ulong dummy)
 {
+	dcache_disable();
+
 	socfpga_init_security_policies();
 	socfpga_sdram_remap_zero();
 
diff --git a/board/altera/arria10-socdk/Kconfig b/board/altera/arria10-socdk/Kconfig
index b80cc6d..621dc97 100644
--- a/board/altera/arria10-socdk/Kconfig
+++ b/board/altera/arria10-socdk/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_SOCFPGA_ARRIA10
+if TARGET_SOCFPGA_ARRIA10_SOCDK
 
 config SYS_CPU
 	default "armv7"
diff --git a/configs/porter_defconfig b/configs/porter_defconfig
index ce309b6..826f78b 100644
--- a/configs/porter_defconfig
+++ b/configs/porter_defconfig
@@ -62,6 +62,7 @@
 CONFIG_RENESAS_SDHI=y
 CONFIG_MTD=y
 CONFIG_MTD_DEVICE=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_MTD=y
@@ -79,6 +80,7 @@
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SCIF_CONSOLE=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_SH_QSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/silk_defconfig b/configs/silk_defconfig
index 0291a7c..09196d7 100644
--- a/configs/silk_defconfig
+++ b/configs/silk_defconfig
@@ -64,6 +64,7 @@
 CONFIG_RENESAS_SDHI=y
 CONFIG_MTD=y
 CONFIG_MTD_DEVICE=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_MTD=y
@@ -81,6 +82,7 @@
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SCIF_CONSOLE=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_SH_QSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/stout_defconfig b/configs/stout_defconfig
index 1c92cb6..552cf55 100644
--- a/configs/stout_defconfig
+++ b/configs/stout_defconfig
@@ -62,6 +62,7 @@
 CONFIG_RENESAS_SDHI=y
 CONFIG_MTD=y
 CONFIG_MTD_DEVICE=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_MTD=y
@@ -79,6 +80,7 @@
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SCIF_CONSOLE=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_SH_QSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c
index 29ea749..1777e7e 100644
--- a/drivers/ddr/altera/sdram_arria10.c
+++ b/drivers/ddr/altera/sdram_arria10.c
@@ -31,7 +31,6 @@
 #define DDR_REG_CORE2SEQ        0xFFD05078
 #define DDR_READ_LATENCY_DELAY	40
 #define DDR_SIZE_2GB_HEX	0x80000000
-#define DDR_MAX_TRIES		0x00100000
 
 #define IO48_MMR_DRAMSTS	0xFFCFA0EC
 #define IO48_MMR_NIOS2_RESERVE0	0xFFCFA110
@@ -103,52 +102,18 @@
 	return 0;
 }
 
-/* Check whether SDRAM is successfully Calibrated */
-static int is_sdram_cal_success(void)
-{
-	return readl(&socfpga_ecc_hmc_base->ddrcalstat);
-}
-
-static unsigned char ddr_get_bit(u32 ereg, unsigned char bit)
-{
-	u32 reg = readl(ereg);
-
-	return (reg & BIT(bit)) ? 1 : 0;
-}
-
-static unsigned char ddr_wait_bit(u32 ereg, u32 bit,
-			   u32 expected, u32 timeout_usec)
-{
-	u32 tmr;
-
-	for (tmr = 0; tmr < timeout_usec; tmr += 100) {
-		udelay(100);
-		WATCHDOG_RESET();
-		if (ddr_get_bit(ereg, bit) == expected)
-			return 0;
-	}
-
-	return 1;
-}
-
 static int emif_clear(void)
 {
-	u32 i = DDR_MAX_TRIES;
-	u8 ret = 0;
-
 	writel(0, DDR_REG_CORE2SEQ);
 
-	do {
-		ret = !wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
-				   SEQ2CORE_MASK, 1, 50, 0);
-	} while (ret && (--i > 0));
-
-	return !i;
+	return wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
+				SEQ2CORE_MASK, 0, 1000, 0);
 }
 
 static int emif_reset(void)
 {
 	u32 c2s, s2c;
+	int ret;
 
 	c2s = readl(DDR_REG_CORE2SEQ);
 	s2c = readl(DDR_REG_SEQ2CORE);
@@ -159,21 +124,28 @@
 	     readl(IO48_MMR_NIOS2_RESERVE2),
 	     readl(IO48_MMR_DRAMSTS));
 
-	if ((s2c & SEQ2CORE_MASK) && emif_clear()) {
-		debug("failed emif_clear()\n");
-		return -EPERM;
+	if (s2c & SEQ2CORE_MASK) {
+		ret = emif_clear();
+		if (ret) {
+			debug("failed emif_clear()\n");
+			return -EPERM;
+		}
 	}
 
 	writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
 
-	if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) {
+	ret = wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
+				SEQ2CORE_INT_RESP_BIT, false, 1000, false);
+	if (ret) {
 		debug("emif_reset failed to see interrupt acknowledge\n");
-		return -EPERM;
-	} else {
-		debug("emif_reset interrupt acknowledged\n");
+		emif_clear();
+		return ret;
 	}
 
-	if (emif_clear()) {
+	mdelay(1);
+
+	ret = emif_clear();
+	if (ret) {
 		debug("emif_clear() failed\n");
 		return -EPERM;
 	}
@@ -189,30 +161,23 @@
 
 static int ddr_setup(void)
 {
-	int i, j, ddr_setup_complete = 0;
+	int i, ret;
 
-	/* Try 3 times to do a calibration */
-	for (i = 0; (i < 3) && !ddr_setup_complete; i++) {
-		WATCHDOG_RESET();
+	/* Try 32 times to do a calibration */
+	for (i = 0; i < 32; i++) {
+		mdelay(500);
+		ret = wait_for_bit_le32(&socfpga_ecc_hmc_base->ddrcalstat,
+					BIT(0), true, 500, false);
+		if (!ret)
+			return 0;
 
-		/* A delay to wait for calibration bit to set */
-		for (j = 0; (j < 10) && !ddr_setup_complete; j++) {
-			mdelay(500);
-			ddr_setup_complete = is_sdram_cal_success();
-		}
-
-		if (!ddr_setup_complete)
-			if (emif_reset())
-				puts("Error: Failed to reset EMIF\n");
+		ret = emif_reset();
+		if (ret)
+			puts("Error: Failed to reset EMIF\n");
 	}
 
-	/* After 3 times trying calibration */
-	if (!ddr_setup_complete) {
-		puts("Error: Could Not Calibrate SDRAM\n");
-		return -EPERM;
-	}
-
-	return 0;
+	puts("Error: Could Not Calibrate SDRAM\n");
+	return -EPERM;
 }
 
 static int sdram_is_ecc_enabled(void)
@@ -270,7 +235,7 @@
 	size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
 		       ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
 
-	debug("SDRAM size=%llu", size);
+	debug("SDRAM size=%llu\n", size);
 
 	return size;
 }
@@ -304,7 +269,7 @@
 	 *	bit[9:6] = Minor Release #
 	 *	bit[14:10] = Major Release #
 	 */
-	if ((socfpga_io48_mmr_base->niosreserve1 >> 6) & 0x1FF) {
+	if ((readl(&socfpga_io48_mmr_base->niosreserve1) >> 6) & 0x1FF) {
 		update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
 		writel(((update_value & 0xFF) >> 5),
 		       &socfpga_ecc_hmc_base->ddrioctrl);
@@ -394,7 +359,7 @@
 			caltim0_cfg_act_to_rdwr -
 			(ctrlcfg0_cfg_ctrl_burst_len >> 2));
 
-	io48_value = ((((socfpga_io48_mmr_base->dramtiming0 &
+	io48_value = ((((readl(&socfpga_io48_mmr_base->dramtiming0) &
 		      ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
 		      (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
 		      /* Up to here was in memory cycles so divide by 2 */
@@ -424,7 +389,7 @@
 		&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
 
 	/* Configure the read latency [0xFFD12414] */
-	writel(((socfpga_io48_mmr_base->dramtiming0 &
+	writel(((readl(&socfpga_io48_mmr_base->dramtiming0) &
 		ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
 		DDR_READ_LATENCY_DELAY,
 		&socfpga_noc_ddr_scheduler_base->
diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h
index d606da8..9213d33 100644
--- a/include/configs/rcar-gen2-common.h
+++ b/include/configs/rcar-gen2-common.h
@@ -53,6 +53,8 @@
 /* SF MTD */
 #if defined(CONFIG_SPI_FLASH_MTD) && !defined(CONFIG_SPL_BUILD)
 #else
+#undef CONFIG_DM_SPI
+#undef CONFIG_DM_SPI_FLASH
 #undef CONFIG_SPI_FLASH_MTD
 #endif
 
diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h
index 06d5d32..20f9821 100644
--- a/include/configs/rcar-gen3-common.h
+++ b/include/configs/rcar-gen3-common.h
@@ -48,7 +48,6 @@
 #define CONFIG_SYS_MONITOR_BASE		0x00000000
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
 #define CONFIG_SYS_BOOTM_LEN		(64 << 20)
 
 /* ENV setting */
diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h
index 58e446b..0f116fb 100644
--- a/include/configs/socfpga_arria10_socdk.h
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -15,8 +15,6 @@
 /*
  * U-Boot general configurations
  */
-/* Cache options */
-#define CONFIG_SYS_DCACHE_OFF
 
 /* Memory configurations  */
 #define PHYS_SDRAM_1_SIZE		0x40000000
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index c9cbf8f..181af9b 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -275,13 +275,20 @@
 
 /* SPL QSPI boot support */
 #ifdef CONFIG_SPL_SPI_SUPPORT
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x40000
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x100000
+#endif
 #endif
 
 /* SPL NAND boot support */
 #ifdef CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x100000
+#endif
 #endif
 
 /*